# 1. Neural network model search (YOSO)
We notice that different neural network models deployed on the same neural network processor exhibit distinct computing efficiency even though the overall sizes are similar. Thereby, smaller neural network models do not promise high computing efficiency on neural network accelerators. With this observation, we propose a co-designed customization framework YOSO that searches for the matched neural network models and neural network accelerator configuration at the same time. Particularly, we propose a novel single-shot AutoML strategy to ensure rapid customization with just the data. YOSO is open sourced and can be found in YOSO directory.
# 2. Compile obtained neural network model
We are still working on the background web server to enable on-line compilation. It will be available soon. Currently, we mainly provide the compiled instructions for a few typical neural networks such that users can try it immediately on Zynq platforms. Table 1 presents the summary of the compiled neural networks and the used dataset. All the neural networks are quantized at 8bit. In addition, note that the models are pre-trained on the open datasets, but they are further tuned for some specific scenarios. The compiled models can be found in model-zoo.
| Neural network models | Datasets |
|---|---|
| Resnet18 | ImageNet2012 |
| Yolo v2 | Pascal VOC |
| Segmentation | CoCo(MS) |
| FaceNet | Webface Vggface2 |
| MTCNN | Wider_face, CelebA |
| K-point | Mpii |
| DCGAN | COCO2014 |
# 3. Add NPU to PL of Zynq
3.1 Since NPU is wrapped as an HDL-based IP, you can add it directly to Zynq PL with Vivado IP integrator. You can refer to Xilinx UG995 for detailed flow of adding user design to IP integrator.
3.2 When the NPU is added to PL side as an accelerator, the design can be synthesized and implemented with Vivado.
3.3 After the implementation, you will get the bitstream file and hadware description file (HDF) which will be used in the next step for booting.
# 4. Boot MZ7100 FPGA board
4.1 To boot the FPGA board, you need to setup MZ7100 properly according to the user manual provided by the board vendors. For ZC706, you may refer to Xilinx UG954. For MZ7100, you can refer to this.
4.2 After the hardware platform setup, we can prepare the BOOT, rootfile system, and linux kernel with Petalinux for booting the board in Linux. Petalinux is a integrated toochain for embedded linux deployment on Xilinx Zynq. Petalinux tutorial can be found at this.
4.3 With petalinux, we can get the rootfile system (boot/rootfs) and the kernel image (boot/kernel). Meanwhile, we can also have the NPU driver and the application compiled with Petalinux with the embedded cross-compiler. The driver and the application can be added to the rootfile system or copied to the FPGA board when the system is booted. The linux diver is located at (boot/driver) and the application demo is located at (boot/app). Finally, we can copy the rootfile system and kernel image to the SD card and boot the FPGA board from SD card.
# 5. Login and run the application
5.1 When the board is booted, you can now connect to the FPGA board with either COM port or ssh. Then you can login the linux system with root.
5.2 Then you can install the driver if it is not automatically launched and run the demo application.